Research Articlevolume 1 Issue 4

Modelling and Simulation of Hetero-Dielectric Junction-less TFET for Low Power Applications

Sagarika Choudhury* and Krishna Lal Baishnab

Published: May 03, 2022

Abstract  

This paper put forwards afresh concept to improvise the conventional JL-TFET. The choice and placement of dielectric are crucial in determining the efficiency of the device. Thus, asymmetric hetero-dielectric is found to improve the gate control and also aid in lowering capacitance. The concept of triple gate material has been incorporated which resulted in better gate control and thereby improving ON-current. The proposed structure reports a current ratio of 4.4 x1010A and promising values for Subthreshold Swing (SS) 9 mV/dec (point) and 48 mV/dec (average).This improvised structure helps in development of devices suitable for low power applications. The simulation based study was performed in July 2021 and compared with the results available.

Keywords: TFET; JLTFET; Hetero-dielectric; Asymmetry